Figure 1 : Sketches of the various solar cells reported in this
work. The c-Si single junction solar cells endowed with p-type and
n-type poly-SiOx CSPCs are shown in the dashed box at
the bottom left. The single-side textured (SST) with front textured and
the double-side textured (DST) solar cells are then combined with 4T
perovskite/c-Si tandem devices. The SST with rear textured solar cell is
used for the 2T perovskite/c-Si tandem device.
Results and discussion
3.1. Passivation properties of poly-SiOx CSPCs
Here, we optimized the passivation quality of n-type and p-type doped
poly-SiOx CSPCs. Since, SST poly-SiOxpassivated c-Si solar cell has n-type doped poly-SiOxCSPC applied on front textured interface and p-type doped
poly-SiOx applied on rear side flat interface, we
optimized n-type doped poly-SiOx CSPC on DST symmetric
samples and p-type doped poly-SiOx on DSP symmetric
samples (see Figure 2(a)). On the other hand, for DST
poly-SiOx passivated c-Si solar cell, we optimize both
n-type and p-type doped poly-SiOx CSPC applied on DST
symmetric samples (see Figure 2(b)). As mentioned earlier in Section
2.1, these CSPCs are prepared stacking doped poly-SiOxlayers on a tunnelling oxide grown by thermal oxidation on a c-Si FZ
wafer, followed by a high temperature annealing step. The passivation
results in Figure 3 were obtained after the high temperature annealing
step. We use two parameters to optimize the passivation of these CSPCs:
(1) the thermal oxidation time for the growth of tunnelling oxide and
(2) the annealing time. Figure 3(a) and (b) show the passivation (in
terms of iVoc) of p-type doped poly-SiOxCSPC applied on DSP symmetrical sample and n-type doped
poly-SiOx applied on DST symmetrical sample,
respectively, for different thermal oxidation time at 675 °C (shown with
different colours). Three annealing times (5, 10 and 15 minutes at 950
°C) were considered for each thermal oxidation time. For both p-type
doped CSPC on DSP wafers and n-type doped poly-SiOx CSPC
on DST wafers, we found the same optimal thermal conditions for the
tunnelling SiOx and the high temperature annealing: 6
minutes at 675 °C and 10 minutes at 950 °C, respectively (see Figure
3(a) for p-type case and Figure 3(b) for n-type case).